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_МЕЖДУНАРОДНЫЙ НАУЧНЫЙ ЖУРНАЛ «ИННОВАЦИОННАЯ НАУКА» №5/2016 ISSN 2410-6070_
Список использованной литературы:
1. Касьяненко Т.Г., Маховикова Г.А, Есипов В.Е., Мирзажанов С.К. Оценка недвижимости: Учебное пособие. Москва: Изд-во КНОРУС, 2011. -752 с.
2. Приказ Минэкономразвития России от 20 мая 2015 г.: № 297 «Об утверждении федерального стандарта оценки "Общие понятия оценки, подходы к оценке и требования к проведению оценки (ФСО №1)". URL: http://economy.gov.ru/minec/activity/sections/corpmanagment/activity/201505218
3. Субботин С.А., Скворцов А.В Использование геоинформационных технологий для ведения земельного кадастра // Вестник Томского государственного университета. 2002. № 275. С. 86-89
© Гинис Л.А., Парфененко Л.А., 2016
UDC 621.389
Gladysheva E.I.
Postgraduate student Moscow Institute of Electronics and Mathematics of National Research University "Higher School of Economics"
Moscow, Russia
ANALYSIS AND SIMULATION OF INFLUENCE OF INTERCONNECTION CONFIGURATIONS ON THERMAL DISSIPATION AND SIZE OF DELAYS OF ULSI AND PCB INTERCONNECT SYSTEMS
Abstract
The study presented in this article deals with the main issues related to the field of reliability and failures of microelectronic devices. The non-uniform temperature profiles along the lines of global interconnect large-scale integrated circuits (LSI) can significantly affect their performance. This article is an in-depth analysis and simulation of device performance degradation due to non-uniform temperature profiles along the length of the existing global lines and through interconnects that occur because of thermal gradients in the base substrate. The impact of changes in configuration for reducing such interconnect parasitic effects of devices as a mismatch of signals in time and deterioration of active elements Performance VLSI and PCB.
Using the software package SolidWorks 2015 different configurations of vias and the temperature distribution along them were simulated. The effects of the influence of the adjacent metal bridges between the metal layers on temperature decrease trunk VLSI were studied. Regarding thermal efficiency the case of the introduction of the aluminum heat sink vias was analyzed and modeled. Produced studies of heat propagation in interconnects of integrated circuits demonstrate the need for including the analysis of thermal conditions of the chip during the various stages of the planning and optimization of high-performance LSI designs, and in their turn they can be easily adapted for practical purposes.
Keywords
Interconnection, through connection, thermal model of the heat sink, fundamental equation of heat conduction, heat
dissipation; geometrical configuration.
In the area of discrete power semiconductors, it is often necessary to analyze the thermal behavior of devices during transients, to anticipate possible failures. This analysis is necessary for a variety of discrete devices (OSFET, high-power bipolar transistor IGBT, Schottky diodes, HFETs), carried out on new materials (eg, SiC, GaN / AlGaN)[1]. These devices, due to their specific properties, are used in products such as SMPS, AC / DC converters and wireless applications of microwave emitters. In the design of printed circuit boards one of the most important tasks is to simulate the delay depending on the heating temperature interconnect. These parameters, which may be varied by PCB designer, are the thickness, width, length and material of LSI interconnects.
_МЕЖДУНАРОДНЫЙ НАУЧНЫЙ ЖУРНАЛ «ИННОВАЦИОННАЯ НАУКА» №5/2016 ISSN 2410-6070_
The main purpose of this study is to investigate the influence of the interconnects and the adjacent metal layers configuration (heat sinks) on the distribution of heat and propagation delays along the lines of global interconnections. To avoid the deterioration of the device performance and premature device failure, Joule heat must be dissipated across the dielectric films into the substrate. There are many factors that affect the heat transfer and thermal distribution in interconnects, such as the thermal conductivity of the dielectric material, the resistivity of metal lines, a current density of metal lines, geometrical parameters and configuration of interconnects.
For one segment of a signal net, there are four possible configurations, depicted in Figure 1, based on the location and connection of the vias. Here, the routes between substrate and metal 1 and between metals 1 and 2 are examined. One can easily extend these configurations in the same manner to the other metal layers. It is assumed that vias get as hot as the layers that are immediately beneath them. In reality, due to their smaller cross sectional area and higher electrical resistivity, vias can become much hotter.
{C} {d}
Figure 1 -Different configurations of interconnect metal lines at layers M1 and M2 and the vias connected at their two ends, in presence of an underlying substrate at temperature Tsub
This study analyzed the case of the interconnection configuration Figure 1b, representing the greatest interest from the practical point of view. For thermal modeling software package SolidWorks 2015 (Figure 2), take interconnection with an rms current of 2 mA in the metal layer with a width of 0.32 m and mainly oxide layer with a thickness of 1.2 mm, length of spread d is approximately 40 microns.
Figure 2 - The result of the thermal simulation of the through connection in SolidWorks 2015
_МЕЖДУНАРОДНЫЙ НАУЧНЫЙ ЖУРНАЛ «ИННОВАЦИОННАЯ НАУКА» №5/2016 ISSN 2410-6070_
To improve heat transport from global interconnects to base substrate, additional dummy metal lines (metal plugs consisting of Cu) acting as heat sinks can be placed[2]. However, dummy metals simultaneously increase the RC constant since they increase the capacitance.
A dielectric constant of 1.3 corresponds to a 0.01W/ m^K dielectric and 1.8 to 0.065 W/ m^K[3]. The resistivity of metal sinks can be approximated by
P T = Psub (1 + a. T (T — rsub)) (1)
, here pT and psub are the metal resistivities at temperature T and base substrate temperature Tsub, respectively. The coefficient aT is the temperature coefficient of resistivity.
For Cu, aT is around 0.004/ °C, which means the resistance of Cu will be increased by around 1.4 if the temperature increases by 100°. Therefore, maintaining a high level of metal line temperature is also important to prevent an increase of a resistive-capacitive time delay. Proper heat developed in the core location of the joint system, it is necessary to avoid unwanted heat effects, such as e-line metal migration and deterioration of the chip. Modeling interconnect with copper heat sink is shown in Figure 3.
I
T
Figure 3 - The result of the thermal simulation of the through connection with copper heat sink in SolidWorks
2015
To calculate the delay in global lines, in this paper, the authors use the model of interconnection in the form of a distributed RC-circuit[4], whose parameters depend on the temperature of the point of interconnection (Figure
4).
Figure 4 - Model of interconnect as a distributed RC circuit. The resistance value R and the capacitance C are dependent on the temperature of the interconnection point Ti. Vin is an input voltage generator, Rg is a resistance
generator, Cload is container load.
The temperature distribution on the surface of the crystal (Figure 5., Figure 6.) is calculated by using the "Overheating -MC" [5]. Parameters of interconnection model (the resistance R (Ti) and the capacitance C (Ti)) and RC circuits were calculated on the bases of the temperature distribution along the interconnection lines.
МЕЖДУНАРОДНЫЙ НАУЧНЫЙ ЖУРНАЛ «ИННОВАЦИОННАЯ НАУКА» №5/2016 ISSN 2410-6070
Figure 5 - The temperature distribution of the crystal along the through interconnection without copper heat sink
Figure 6 - The temperature distribution of the crystal along the through interconnection with copper heat sink
_МЕЖДУНАРОДНЫЙ НАУЧНЫЙ ЖУРНАЛ «ИННОВАЦИОННАЯ НАУКА» №5/2016 ISSN 2410-6070_
Program for calculating the parameters of the model "Overheating -MC" shows the calculation results in a description of the circuitry in the format of SPICE. Based on the data obtained in the SPICE delays were calculated.
The propagation delay of the signal in the interconnection without the inclusion of a copper heat sink inhomogeneous temperature profile was 33.08 ps, the delay into account the copper heat sink c 26.13 ps, ie, error is 21%.
Conclusions
According to the above study, the configuration and geometry of the metal lines have a strong influence on the heat transfer ability of interconnect systems. Therefore, they must be very carefully planned. The results obtained in this study include qualitative assessments of the heat dissipation of such structures. Electrical resistivity and thermal conductivity of copper embedded webs are decisive factors in the heat transfer in VLSI interconnects at a certain power level. It is found out that the delay of the nonuniform heat distribution configuration in use with metal heatsink 21% less than for the same interconnect without introducing additional fictitious copper heat sink.
This situation would be much more serious for the global line consisting of more than two layers. The results of this approach can be effectively used for two practically important purposes: firstly, for improving the electric characteristics and thermal conditions existing IC (i.e. their upgrading) and, secondly, for developing a new IC, optimal from the point of thermal conditions, where the negative impact of thermal effects are minimized.rm heat distribution configuration in use with metal heatsink 21% less than for the same interconnect without introducing additional fictitious copper heat sink. References:
1. Gladysheva E.I., N.I. Ryabov, Calculation and simulation of interconnects in GaAs 4-bit adder considering temperature effects, Science in the modern information society, North Charleston, USA, March 2016, 99-104.
2. Gladysheva E.I., N.I. Ryabov, The simulation of delays in IC interconnects considering temperature effects, Actual problems technical sciences in Russia and abroad, September 10, 2015, 3-5;
3. Xiao Xi,Yao Suying,Ruan Gang, Influence of interconnection configuration on thermal dissipation of ULSI interconnect systems Article in Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 27(3): March 2006,516523;
4. Amir H. Ajami, Member, Kaustav Banerjee, Senior Member, and Massoud Pedram, Fellow Modeling and Analysis of Nonuniform Substrate Temperature Effects on Global ULSI Interconnects IEEE Trans. on comp.- aided design of intergrated circ. and sys., V. 24, NO. 6, JUNE 2005 849-860;
5. Petrosyants KO, Ryabov NI The computer program "Overheating MC." The certificate number 2007613306 from 6.08.2007 of the official registration of the computer program.
The article was prepared within the framework of a subsidy granted to the National Research University Higher School of Economics by the Government of the Russian Federation for the implementation of the Global Competitiveness Program, Moscow Institute of Electronics and Mathematics.
©Gladysheva E.I.., 2016
УДК 658.562.012.7
Я.А. Деянова
Студентка 2 курса магистратуры РГАУ - МСХА имени К.А. Тимирязева, г. Москва РФ
РАЗРАБОТКА РАБОЧЕГО ЛИСТА ХАССТ ДЛЯ МОНИТОРИНГА ПРОЦЕССА ПРОИЗВОДСТВА НАТУРАЛЬНЫХ ПОЛУФАБРИКАТОВ ИЗ МЯСА ПТИЦ
Аннотация
В статье проводится методика анализа качества и назначение контрольных точек при производстве натуральных полуфабрикатов из мяса птицы. Разработана форма рабочего листа ХАССП.
